A complementary MOS (CMOS) is an MOS (metal oxide semiconductor) circuit formed with both N-channel and P-channel transistors. This type of semiconductor circuit is used to produce high performance devices without high power consumption. CMOS technology also allows circuits to be formed on one chip that would otherwise require several chips using N-channel and P-channel only circuits. A Bi-MOS circuit combines bipolar, P-channel, and N-channel transistors along with memory cells.
A representative CMOS device is disclosed in FIG. 1. The CMOS device 10 is formed on a wafer substrate 12 and includes an N-channel transistor 14 and a P-channel transistor 16. Each transistor 14,16 includes a source/drain 18, a gate 20, and a gate oxide 22. A P-well 26 is formed in the substrate 10 for the N-channel transistor 14, and an N-well 28 for the P-channel transistor 16.
CMOS devices 10 are formed by first fabricating the N-channel MOS transistor -4 in the deep P-well 26 formed in the wafer substrate 12. After N-channel transistor 14 formation, the P-channel transistor -6 is fabricated. To do so, two different photo masking steps are required to cover the N-channel area of the substrate 12 while tailoring the P-channel structure, and to cover the P-channel structure while tailoring the N-channel structure. This requires extra masks in addition to the already large number of masks required (i.e., PTUB mask, thin oxide mask, polysilicon mask, P-plus mask (positive), P-plus mask (negative), contact mask, metal mask). Moreover, each masking step requires the use of chip areas which otherwise could be occupied by the devices ultimately formed in the chip. Finally, lithographic masking steps require extreme precision and registration during formation thereof. Each additional lithographic masking step in a process introduces possible masking defects and increases mask-to-mask registration problems that decrease the processing yield and, accordingly, significantly increases the fabrication cost. A basic objective in IC fabrication is to minimize the number of basic lithographic masking steps required to produce a particular integrated circuit array of device structures.
Prior art manufacturing techniques have resulted in overly complicated manufacturing processes requiring numerous time-consuming and costly processing steps. Therefore, there is an ever increasing need for a semiconductor manufacturing process in which CMOS and Bi-MOS devices can be fabricated with a simplified process.
U.S. Pat. No. 4,558,508 to Kinney et al., discloses a semiconductor manufacturing process in which only a single lithographic masking step is required for providing self alignment both of the wells to each other and also of the field isolation doping regions to the wells. In the Kinney et al. disclosure, the lithographic masking step forms a well mask and defines an oxidation barrier which acts as an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field doping regions; and a dopant transmitter during the ion implantation of an opposite type field dopant which is simultaneously absorbed by the sacrificial oxide.
Other processes for forming a self-aligned mask which eliminate separate masks for forming N-channel and P-channel devices in a semiconductor wafer are disclosed in U.S. Pat. No. 4,471,523 to Hu; U.S. Pat. No. 4,868,135 to Ogura et al; U.S. Pat. No. 4,480,375 to Cottrell et al.; U.S. Pat. No. 4,470,191 to Cottrell et al.; U.S. Pat. No. 4,462,151 to Geipel, Jr. et al.; U.S. Pat. No. 4,843,023 to Chin et al.; U.S. Pat. No. 4,509,991 to Taur; and U.S. Pat. No. 4,795,716 to Yilmax et al.
The present invention is directed to a process for the fabrication of CMOS devices wherein during manufacture an inverse self-aligned mask is formed using chemical mechanical polishing technology to isolate and align separate N-channel and P-channel areas of the substrates. The method of the invention simplifies the process for manufacturing such semiconductor devices by eliminating separate masking steps.